An apparatus such as a television set and a set-top box for processing high-quality video data and audio data generally encrypts its data for transmission in order to prevent illegal copying and data tampering. For such encryption and decryption purposes, a nonvolatile memory device may be embedded that stores a device unique ID and/or a communication key in a rewritable manner.
In order to prevent encryption from being decoded through illegal means, provision is made such that data stored in a nonvolatile memory may not be easily read for purposes other than the intended purpose. A memory that has a mechanism for protecting the security of data contents is referred to as a secure memory.
In a configuration in which a secure memory is mounted in an SoC (System on Chip), there are conflicting requirements, i.e., a requirement to prohibit the stored data from being read for the purpose of protecting its security and a requirement to read the stored data for the purpose of checking the correctness of written data. A means to check the correctness of stored data while maintaining a high security level includes a check mechanism that utilizes a CRC (Cyclic Redundancy Check) method, a parity method, a check-sum method, or the like to indirectly check data correctness without actually retrieving the data to be checked. Such a check mechanism, however, may not be able to detect error for some types of data failures. Further, a need to correct an error in addition to detecting an error, if such a need exists, may result in an increase in circuit complexity and a drop in processing speed. In addition, the error correction ability may not be satisfactory.
When a secure memory is implemented in an SoC, it is preferable to easily and reliably perform tasks such as writing data, checking data, and correcting error at the time of chip tests prior to shipment. The error detection and correction mechanism as noted above may thus not be a preferable data check means to be used for a secure memory in an SoC. Related arts are described in Japanese Patent Application Publication No. 10-314451, Japanese Patent Application Publication No. 04-168700, Japanese Patent Application Publication No. 01-118933 and Japanese Patent Application Publication No. 01-279344.